发明名称 Timing circuits with improved power supply jitter isolation technical background
摘要 In accordance with the invention, feed forward compensation of jitter induced by power supply noise is incorporated into the negative feedback control loop of a timing synchronization circuit, such as a phase locked loop or delay locked loop. More particularly, the dependence of the circuitry in the negative feedback loop, such as the delay elements in a DLL or the oscillator in a PLL, to fluctuations in the power supply are counteracted by introducing into the feedback loop a signal component that is a function of the supply voltage and that will have the opposite effect from any direct fluctuations in the power supply voltage.
申请公布号 US2007096783(A1) 申请公布日期 2007.05.03
申请号 US20050260805 申请日期 2005.10.27
申请人 AGERE SYSTEMS INC. 发明人 DE LA TORRE LUIS
分类号 H03L7/06 主分类号 H03L7/06
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