Systems and methods for performing profile-based circuit optimization using high-level system modeling

摘要

Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL. The design system may generate the optimized configuration data without performing multiple, time-consuming, HDL compilations.

主权项

1. A method of using logic design computing equipment to design a logic circuit for implementing on a target device that is separate from the logic design computing equipment, the method comprising:
with an emulation engine on the logic design computing equipment, receiving a computer program language description of the logic circuit, modeling performance of the target device when loaded to implement the logic circuit identified by the computer program language description prior to implementing the logic design on the target device, and generating statistics based on the modeled performance of the target device when loaded to implement the logic circuit; with a first compiler on the logic design computing equipment, generating an optimized hardware description language (HDL) description of the logic circuit based on the generated statistics; with a second compiler on the logic design computing equipment, generating an optimized configuration data bit stream for the target device by compiling the optimized HDL description of the logic circuit; and with a configuration device, loading the optimized configuration data bit stream onto the target device, wherein the target device implements the logic circuit as identified by the optimized HDL description when loaded with the optimized configuration data bit stream.