INTERNAL CONSECUTIVE ROW ACCESS FOR LONG BURST LENGTH

摘要

A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.