| 摘要 |
PURPOSE:To decrease the circuit scale by providing the 1st and 2nd means converting 0 or 1 of a binary input data to a prescribed level, converting code by both means and transferring data so as to transmit simultaneously data and clock independently of a transmission speed. CONSTITUTION:An input data is inputted to AND circuits 1, 2, 6 and an NAND circuit 5 of a data transfer system and a clock is inputted to the circuits 1, 2, 6 and an AND circuit 8. Further, an output of the circuits 1, 2 is supplied to a clock and a reset terminal of an FF4, an output of the FF4 is inputted to the circuit 5 and a data terminal of the FF4 and an output of the circuits 6, 8 is supplied to a base of transistor (TRs) 1, 2 respectively. Then, ''0'' of the binary input data is converted to +1, -1 level and 1 is converted to +1, 0 level and when 1s are consecutive, 1 is converted to +1 level and -1 level alternately. The data is code-converted by this conversion and the data is transmitted to transfer simultaneously the data and clock information independently of a transmission speed. |
