发明名称
摘要 PURPOSE:To shorten the time of computation by easily performing the various arithmetic of pool matrix by combining arithmetic, realized by hardware, with the function of controlling the execution easily. CONSTITUTION:From external interface 1, control circuit 2 is supplied with the initial value of a pool matrix, assignment information on whether the arithmetic of arithmetic circuit 5 is the pool sum or pool product, and extent assignment information for arithmetic on the pool matrix. Through input-output circuit 3, circuit 2 sets the initial value of the pool matrix in pool matrix memory circuit 4 stored with every element of the pool matrix and also sends assignment information on the sort of arithmetic to circuit 5. According to the assignment information on the extent of arithmetic, circuit 2 sends a certain row of the pool matrix from pool matrix memory circuit 4 to circuit 5 via circuit 3 and its output is sent to circuit 4 to modify the contents of the pool matrix repeatedly, thereby making it easy to perform various arithmetic of the pool matrix.
申请公布号 JPS6152513(B2) 申请公布日期 1986.11.13
申请号 JP19790051961 申请日期 1979.04.26
申请人 NIPPON ELECTRIC CO 发明人 MYASHITA YOICHI
分类号 G06F17/16;G06F15/78 主分类号 G06F17/16
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