| 摘要 |
PURPOSE:To decrease the number of steps when a physical address is produced by using an all-0 detecting circuit to whether the low-order N bits in a base address set at a base address register are equal to all-0 or not. CONSTITUTION:An all=0 detecting circuit 6 detects that the low-order N bits of a base address stored in a base address register 3 are equal to all-0. In such a case, the contents of physical address register 5 which are obtained from merging are defined as a desired physical address. If it is decided that low-order N bit are not equal to all-0, the result of addition of an adder 7 is stored in the register 5 as a desired physical address. As a result, the coincidence is secured between the output of the adder 7 and the data to be set at the register 5 if said low-order N bit are equal to all-0. Thus no addition arithmetic is needed when the low-order bits of the base address are equal to all-0 and therefore the processing speed is increased.
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