| 摘要 |
PURPOSE:To prevent a malfunction even if the false synchronism or the flaw if a vertical synchronizing signal is inputted by providing a flip flop, which holds the flip flop for generating a frame signal, at a set state. CONSTITUTION:The vertical synchronizing signal, a composite synchronism, the clock of 1H period and a set release pulse are inputted to a terminal 10, the terminal 11 the terminal 17 and the terminal 19, respectively. A video signal is assumed to be an NTSC, and the frame signal which comes to a high level and a low level at an odd field and an even field, respectively is assumed to be outputted. In case of the odd field, the timings of the respective signals come as shown in a figure. Even it the output Q of the flip flop (F/F) 14 returns to the high level, the output Q of the F/F 16 is held at the low level till the next set release pulse 19 is inputted, and consequently, because the F/F 13 is held at the set state as well, the malfunction is prevented during a hold duration against a disorder such as the flaw of the vertical synchronizing signal 10 and the composite synchronism 11, etc. As for the even field, it is similar.
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