| 摘要 |
A circuit for synchronizing the phase output of a clock relative to multiple asynchronous input trigger signals. A clock signal is directed as an input to a delay line having spaced output taps to produce a plurality of phase displaced clock signals, which are directed as inputs to a latch circuit. An input trigger signal causes the latch circuit to latch the current states of the phase displaced clock signals, which are directed as inputs to a programmable array logic circuit. Based upon the states of the clock signals, the logic circuit selects the particular clock signal which is synchronized with the input trigger signal, and that particular clock signal is gated as the output clock signal.
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