发明名称 THIN-FILM TRANSISTOR ARRAY AND MANUFACTURE THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To provide an inter-layer insulated-film structure and a manufacturing method thereof which prevent inter-layer leakage while maintaining capacitance of a predetermined amount or greater between an auxiliary capacitance electrode and a source drain electrode, and further, improve selective adhesion of P(phosphorus) in PH3 plasma processing. SOLUTION: An auxiliary capacitance electrode 2 is formed by using a conductive film on an insulated substrate 1, and inter-layer insulated films are formed between the auxiliary capacitance electrode 2 and a source drain electrode 6 formed thereon. An upper film of the inter-layer insulated films is formed of a silicon oxide film 4, and a lower film is formed of an insulated film 3 having a permittivity higher than that of the silicon oxide film 4 of the upper film. This prevents inter-layer leakage while maintaining a great capacitance between the auxiliary capacitance electrode 2 and the source drain electrode 6. Further, as a back channel portion under the source drain electrode 6 is the silicon oxide film 4, improved selective adhesion of P(phosphorus) is attained in plasma processing. Thus, a thin-film transistor array having an excellent transistor characteristic can be obtained.</p>
申请公布号 JPH09153617(A) 申请公布日期 1997.06.10
申请号 JP19950311237 申请日期 1995.11.29
申请人 NEC CORP 发明人 NAKADA SHINICHI
分类号 G02F1/136;G02F1/1368;H01L29/786;(IPC1-7):H01L29/786 主分类号 G02F1/136
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