Memory Circuit and Cache Circuit Configuration

摘要

A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

主权项

1. A method of operating a memory circuit, the memory circuit comprising a primary memory circuit and a cache memory circuit, the primary memory circuit having P access channels of Q bits of channel bandwidth, the cache memory circuit having P subsets of Q*N memory cells, P and Q being integers greater than 1, N being a positive integer, and the method comprising:
determining, in response to a read command for reading a first data accessible through a first access channel of the primary memory circuit and a second data accessible through a second access channel of the primary memory circuit, if a valid duplication of the first data and the second data is stored in the cache memory circuit; storing a duplication of Q*n bits of consecutively addressed data from the first access channel and a duplication of Q*n bits of consecutively addressed data from the second access channel to the cache memory circuit, if the valid duplication of the first data and the second data requested by the read command is not stored in the cache memory circuit, n being an integer from 1 to N; and outputting the first data and the second data from the cache memory circuit if the valid duplication of the first data and the second data is stored in the cache memory circuit.