| 摘要 |
PURPOSE:To obtain a two-phase clock pulse generator which has high reliability, and is easily designed, by preventing the two-phase clock pulses from being set at significant levels at one time with use of an inverter, R-SFF circuit, delaying circuit and a logical circuit. CONSTITUTION:A single-phase clock pulse phi is applied to the input of an inverter 81 as the input signal. The output of the inverter 81 and the pulse phi are fed to an R-SFF circuit comprising NAND gates 83 and 82. Thus two-phase clock pulses (c) and (d) are obtained and then supplied to an end of the NOR gates 85 and 84 respectively. At the same time, the pulse (d) is supplied to the other end of the gate 85 via an inverter 86, and the pulse (d) is supplied to the other end of the gate 84 via inverters 86 and 87. Then two-phase clock pulses (g) and (h) which are not set at significant levels at one time are obtained from both output terminals of the gates 84 and 85. Such circuit is designed easily for integration and excels in reliability since no adjustment is required. |
