发明名称 CAPACITOR PRECHARGE FOR REDUCED SYNTHESIZER LOCK TIME
摘要 CAPACITOR PRECHARGE FOR REDUCED SYNTHESIZER LOCK TIME of the Invention A method and process for reducing the frequency lockon time required for a radiotelephone transitioning from a standby mode to a normal operation mode. The present invention comprises a microphone (101) coupled to a transmit synthesizer (104) through audio circuitry (102), a reference oscillator (103), and a transistor switch (109) controlled by a processing device (110). The transmit synthesizer (104) is comprised of a phase detector (105) coupled to a loop filter (106) that is coupled to a voltage controlled oscillator (VCO) (107). The output of the VCO (107), which is also the output of the present invention, is fed back through a divide by N (108) to the phase detector. The microcomputer (110), in the standby mode, periodically switches on power to the transmit synthesizer (104), keeping a capacitor in the loop filter (106) charged and thereby maintaining the voltage applied to the VCO (107). This voltage determines the frequency of the signal produced by the VCO (107). If this voltage is kept at the level used during normal operation, when the radiotelephone goes from standby to normal, this voltage will be close to the proper level.
申请公布号 CA2033747(A1) 申请公布日期 1991.07.20
申请号 CA19912033747 申请日期 1991.01.11
申请人 MOTOROLA, INC. 发明人 BARABAN, JAMES P.;MOLLER, PAUL J.;SKUTTA, FRANK R.
分类号 H03C3/09;H03L3/00;H03L7/08;H03L7/10;(IPC1-7):H03L7/10 主分类号 H03C3/09
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