| 摘要 |
A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device. The N-type well region functions to absorb or capture hot electrons generated by the N-channel MOS transistor of the CMOS peripheral circuit, and the P-type minority carrier absorption semiconductor region functions to absorb or capture holes which would otherwise combine with the hot electrons to induce substrate current which could deleteriously lower the threshold voltage level of the memory cells of the memory array and thereby degrade the data storage integrity thereof.
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