| 发明名称 |
Semiconductor arrangement used for large scale integrated circuits |
| 摘要 |
Semiconductor arrangement has a silicide protective section (8) made up of several insulating layers (81, 82, 83) that covers a gate isolation layer (4), a gate electrode (6) and a side wall (5) covering the side surfaces of the gate insulating layer and the side surfaces of the gate electrode.
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| 申请公布号 |
FR2778495(A1) |
申请公布日期 |
1999.11.12 |
| 申请号 |
FR19980014151 |
申请日期 |
1998.11.10 |
| 申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HIRANO YUUICHI;YAMAGUCHI YASUO;MAEGAWA SHIGETO |
| 分类号 |
H01L21/302;H01L21/3065;H01L21/336;H01L29/78;H01L29/786;(IPC1-7):H01L21/56 |
主分类号 |
H01L21/302 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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