Dynamically improving performance of a host memory controller and a memory device

摘要

Methods, apparatuses, systems, and computer-readable media for dynamically improving performance of a host memory controller and a hosted memory device are presented. According to one or more aspects, a memory controller may establish a data connection with a memory device. The memory controller may perform a first write operation of a plurality of write operations to the memory device using a first block size. Subsequently, the memory controller may perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size. The memory controller then may determine an optimal value for a block size parameter based at least in part on the plurality of write operations. Thereafter, the memory controller may use the optimal value for the block size parameter in performing one or more regular tasks involving the memory device.

主权项

1. A method comprising:
establishing, by a memory controller, a data connection with a memory device, the memory device adhering to a common standard as the memory controller; determining, by the memory controller, whether the memory device is recognized or not and, upon determining that the memory device is not recognized:
(i) performing, by the memory controller, a first write operation of a plurality of write operations to the memory device using a first block size;(ii) performing, by the memory controller, a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size, wherein the first block size and the second block size are included in a sweep pattern of different block sizes, the sweep pattern determined based on at least one of: (a) the standard or (b) one or more modes of the standard;(iii) determining, by the memory controller, an optimal value for a block size parameter associated with the memory device based at least in part on the plurality of write operations; and(iv) storing, by the memory controller, the optimal value for the block size parameter associated with the memory device, the stored optimal value associated with the memory device retrievable upon recognition of the memory device; and using, by the memory controller, a stored optimal value for a block size parameter associated with the memory device in performing one or more regular tasks involving the memory device, wherein a first optimal value is determined for a first mode of operation defined by the standard, and wherein a second optimal value is determined for a second mode of operation defined by the standard, the second mode being different from the first mode.