| 发明名称 | Semiconductor memory device including output buffer | ||
| 摘要 | An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal. | ||
| 申请公布号 | US9627013(B2) | 申请公布日期 | 2017.04.18 |
| 申请号 | US201514622520 | 申请日期 | 2015.02.13 |
| 申请人 | Micron Technology, Inc. | 发明人 | Takeda Hiromasa;Fujisawa Hiroki |
| 分类号 | G11C7/10;G11C7/04;G11C29/02 | 主分类号 | G11C7/10 |
| 代理机构 | Dorsey & Whitney LLP | 代理人 | Dorsey & Whitney LLP |
| 主权项 | 1. An apparatus comprising: a first terminal configured to communicate data with an outside of the apparatus; a second terminal configured to receive a first power source potential; a third terminal configured to receive a second power source potential different from the first power source potential, wherein the first to third terminals are arranged on a line such that the first terminal is positioned between the second and third terminals; a fourth terminal configured to be coupled to a calibration resistor, wherein the fourth terminal is arranged adjacently to the second terminal such that the second terminal is on the line between the first and fourth terminals; an output buffer including first to third nodes coupled to the first to third terminals respectively; and a replica circuit including fourth, fifth nodes coupled to the second and third terminals respectively, and further including a sixth node coupled to the fourth terminal. | ||
| 地址 | Boise ID US | ||