Pipe latch Circuit for output data with high speed in Sychronous Memory device and Synchronous Memory device using the same,申请号KR20020046503-传众专利搜索

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发明名称	Pipe latch Circuit for output data with high speed in Sychronous Memory device and Synchronous Memory device using the same
摘要
申请公布号	KR100484249(B1)	申请公布日期	2005.04.22
申请号	KR20020046503	申请日期	2002.08.07
申请人		发明人
分类号	G11C11/407;(IPC1-7):G11C11/407	主分类号	G11C11/407
代理机构		代理人
主权项
地址

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