Data processing apparatus with fixed address space and variable memory.

摘要

A CPU initialises pluggable adapters with built-in identity and conditional ROS and compiles an HFLIH table of identity against status register address and an SFLIH table of identity against on-board system function. It stores the tables with a control module in enabled memory on the keyboard adapter. Conditional ROS is enabled on any adapter receiving a broadcast of its own identity. Adapter interrupts are ORed. HFLIH is stepped through by the control module to access adapter status sequentially, servicing each adapter in turn from its ROS, using its broadcast identity. System functions are accessed via SFLIH.