发明名称 |
RELIABILITY, AVAILABILITY, AND SERVICEABILITY IN MULTI-NODE SYSTEMS WITH DISAGGREGATED MEMORY |
摘要 |
A shared memory controller receives a memory access request from a computing node, the request corresponding to a particular line of pooled memory. An error corresponding to the request is identified and the request is forwarded to a second shared memory controller in response to the error. A response is received to the request from the second shared memory controller. The response can be forwarded to the computing node by the shared memory controller. |
申请公布号 |
US2016283303(A1) |
申请公布日期 |
2016.09.29 |
申请号 |
US201514671881 |
申请日期 |
2015.03.27 |
申请人 |
Intel Corporation |
发明人 |
Sharma Debendra Das;Jen Michelle C. |
分类号 |
G06F11/07;G06F3/06 |
主分类号 |
G06F11/07 |
代理机构 |
|
代理人 |
|
主权项 |
1. An apparatus comprising:
a first shared memory controller to control access to a portion of a memory pool, wherein the first shared memory controller comprises:
a first interface to receive a memory access request from a computing node, wherein the request corresponds to a particular line of pooled memory;error detection logic to identify an error corresponding to the request;a second interface to:
send the request to a second shared memory controller in response to the error;receive a response to the request from the second shared memory controller, wherein the first interface is further to forward the response to the computing node. |
地址 |
Santa Clara CA US |