发明名称 Circuit for generating regulated output voltage from unregulated input voltage
摘要 The unregulated input voltage (U) is introduced via an input connection (1) and the regulated output voltage (VDD) is tapped from an output connection (2). The load current path of a transistor (3) is connected between the input and output connections. The regulated output voltage is fed to a control amplifier (4) whose output is coupled to the transistor's control connection via a capacitor (8). The capacitor is discharged by a current source (7) controlled by the control amplifier. A charge pump (5) has an output for a raised voltage connected to the transistor's control connection and its output voltage is controlled by the control amplifier.
申请公布号 DE4442466(C1) 申请公布日期 1995.12.14
申请号 DE19944442466 申请日期 1994.11.29
申请人 SIEMENS AG, 80333 MUENCHEN, DE 发明人 FELDTKELLER, MARTIN, DIPL.-ING., 81543 MUENCHEN, DE
分类号 G05F1/56;(IPC1-7):G05F1/56 主分类号 G05F1/56
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