Test mode entry interlock

摘要

An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.

主权项

1. An integrated circuit device, comprising:
a first terminal for receiving an externally supplied voltage to force the first terminal to a first logic state; an input/output buffer coupled to the first terminal, comprising:
an output buffer connected to drive the first terminal to a second logic state in response to a command input provided to the output buffer, andan input buffer connected to convey a detected logic state from the first terminal as a first input signal in response to the externally supplied voltage being received at the first terminal; a second terminal circuit for receiving a special mode entry command that is independent from the externally supplied voltage and for generating a second input signal; and an evaluation circuit for generating a special mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the second logic state.