| 摘要 |
PURPOSE: A high-speed level converter is provided which minimizes data transmission delay created in a level converter of a semiconductor device to enable high-speed access of data. CONSTITUTION: A level converter includes a data input unit(300) for receiving data and outputting the data in synchronization with a converted clock signal(Clock), a clock level converter(400) for converting the level of the clock signal into an external power voltage level, and a level conversion and latch unit(500) for receiving the data from the data input unit, level-converting and latching the data according to the output signal of the clock level converter and the clock signal. The transmission logic path of data output at the rising edge of the clock signal is reduced to improve level conversion speed of data.
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