Computing system automatically generating a transactor

摘要

A computing system includes a memory device into which a design file for a predetermined intellectual property (IP) and a transactor generating tool are loaded, and a processor configured to execute the transactor generating tool loaded into the memory device. The transactor generating tool executed by the processor extracts port information of the IP from the design file, and generates at least one transactor corresponding to the IP based on the port information.

主权项

1. A system-on-chip (SoC) bus verification device for verifying a bus of an SoC, comprising:
a memory device configured to store a file list for the SoC including a design file associated with an intellectual property (IP) and a transactor generating tool; and a processor configured to execute the transactor generating tool stored in the memory device, wherein the transactor generating tool when executed by the processor causes the processor to:
extract port information for the IP from the design file;generate at least one transactor associated with the IP based on the port information; andreplace the design file of the IP included in the file list for the SoC with an empty design file and the generated transactor.