| 摘要 |
PURPOSE:To improve inter-layer insulation by dipping a semiconductor substrate in an etching liquid in a patterning process for a metallic wiring layer and etching said substrate under decompression when multilayer interconnections are formed on the semiconductor substrate. CONSTITUTION:Silicon dioxide 22 with contact holes are formed on a silicon substrate 21, and first layer wiring metals 23 are shaped on the silicon dioxide 22. A first insulating film 24 to which first through-holes 25 are formed and a second layer wiring metallic layer 26 are formed on the wiring metals 23 in succession. Third layer wiring metallic layers 29 are shaped similarly on the whole surface of a second insulating film 27. A resist is applied on the wiring metallic layers 29, and exposed and developed, thus patterning the film 27. Lastly, a wafer to which these treatment is executed is dipped in a wet type etching liquid, and the pressure of the outside air is decompressed to 1Torr or less and the wafer is etched. Accordingly, the remaining of the wiring metal at a stepped section generated on etching is prevented, and the generation of a short circuit, etc. among the metallic wirings can be obviated. |
