| 摘要 |
<p>A switch and decoder circuit and method of reading same includes a 4 to 16 line decoder latch (18) for selectively enabling up to 14 manually settable switches (12), each of which generates a BCD code in response to a switch setting, a plurality of thumb wheel switches each of which is selectively enabled by the decoder latch (18) are connected in parallel to a data bus which can then be sensed by associated circuitry. Two pseudoswitches are provided which may be selectively enabled by the decoder latch and which gate onto the address bus two known, non-BCD codes for hardware checking purposes. A control program in an associated processing unit through input/output circuitry can select a switch whose outputs are to be sensed, read asserted and negated values for the switch, compare the values to a predetermined range of allowable values, and cycle the pseudoswitches to determine whether or not the hardware is functioning properly.</p> |
