ENFORCING DATA PROTECTION IN AN INTERCONNECT

摘要

Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

主权项

1. Interconnect circuitry comprising:
transaction coherency circuitry responsive to a memory transaction received from a first master device, wherein the memory transaction specifies a transaction target in a memory and a coherency type, to cause a snoop access to be transmitted to a cache of a second master device in dependence on the coherency type and, when a memory accessing transaction is received from the second master device in order to maintain coherency of a copy of the transaction target in the cache, to transmit the memory accessing transaction to a memory protection controller which is arranged to police access to the memory; and transaction monitoring circuitry responsive to reception of the memory transaction from the first master to modify the coherency type to a memory accessing coherency type, wherein the transaction coherency circuitry is responsive to the memory accessing coherency type to initiate an access to the transaction target in the memory when a modified version of the copy of the transaction target is in the cache.