发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technique that can reduce warpage in a wafer by decreasing the film stress of an entire interlayer insulating film. SOLUTION: The interlayer insulating film TH4 between third and fourth layer wiring M3 and M4 is set to the laminated structure film of a TEOS film TH4a formed by the CVD method, an SOG film TH4b formed by applying an SOG film onto the TEOS film TH4a and by performing heat treatment, and a TEOS film TH4c formed on the SOG film TH4b. By making films laminated, the film stress in each film is canceled, and hence the warpage in the wafer is reduced.
申请公布号 JP2002033386(A) 申请公布日期 2002.01.31
申请号 JP20000214991 申请日期 2000.07.14
申请人 HITACHI LTD 发明人 TORII KATSUHIRO;FUJIWARA TAKESHI;MARUYAMA HIROYUKI
分类号 C23C16/40;H01L21/316;H01L21/768;H01L23/522;(IPC1-7):H01L21/768 主分类号 C23C16/40
代理机构 代理人
主权项
地址