PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS
摘要
A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
申请公布号
WO0227799(A2)
申请公布日期
2002.04.04
申请号
WO2001GB04154
申请日期
2001.09.17
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED
发明人
BOYD, DIANE, CATHERINE;BRODSKY, STEPHEN, BRUCE;HANAFI, HUSSEIN, IBRAHIM;ROY, RONNEN, ANDREW