发明名称 |
Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes |
摘要 |
A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed. |
申请公布号 |
US9502313(B1) |
申请公布日期 |
2016.11.22 |
申请号 |
US201615060008 |
申请日期 |
2016.03.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Basker Veeraraghavan S.;Bu Huiming;Yamashita Tenko |
分类号 |
H01L21/308;H01L21/84;H01L29/66;H01L49/02;H01L21/265;H01L21/02 |
主分类号 |
H01L21/308 |
代理机构 |
Cantor Colburn LLP |
代理人 |
Cantor Colburn LLP ;Alexanian Vazken |
主权项 |
1. A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices, the method comprising:
forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a conformal oxide layer having a thickness of about 2-4 nanometers on the semiconductor fins, the buried oxide layer, and the trench; forming a polysilicon layer having a thickness of about 30-100 nanometers over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an oxide layer over the polysilicon layer; planarizing the oxide layer and the polysilicon layer so as to remove the oxide layer, except for a portion of the oxide layer formed in the depression, thereby defining a protective oxide island directly over a portion of the polysilicon layer corresponding to a location of the polysilicon resistor; forming a nitride hardmask over the polysilicon layer and the protective oxide island; patterning the hardmask and etching the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; forming a patterned resist layer to protect the semiconductor fins; performing an ion implantation with boron to dope the polysilicon resistor; depositing a high density plasma (HDP) oxide layer and planarizing the HDP layer to expose the patterned hardmask layer; removing the patterned hardmask layer and etching the exposed polysilicon layer to remove the dummy gate structure, wherein the protective oxide island prevents the polysilicon resistor from being removed; removing the conformal oxide layer; forming one or more replacement metal gate stack layers over the fins; and planarizing the metal gate stack layers to define a finFET area and a doped polysilicon resistor. |
地址 |
Armonk NY US |