发明名称 |
HIGH ELECTRON MOBILITY TRANSISTORS WITH LOCALIZED SUB-FIN ISOLATION |
摘要 |
Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process. |
申请公布号 |
WO2016209278(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
WO2015US38069 |
申请日期 |
2015.06.26 |
申请人 |
INTEL CORPORATION |
发明人 |
RACHMADY, Willy;METZ, Matthew V.;DEWEY, Gilbert;MOHAPATRA, Chandra S.;KAVALIEROS, Jack T.;MURTHY, Anand S.;GHANI, Tahir;RAHHAL-ORABI, Nadia M.;GARDNER, Sanaz K. |
分类号 |
H01L29/78;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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