Low-power low density parity check decoding

摘要

In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.

主权项

1. A system comprising:
message passing low density parity check (LDPC) decoder circuitry comprising:
circuitry configured to implement a plurality of LDPC variable nodes;circuitry configured to implement a plurality of LDPC check nodes;a plurality of variable node lock registers, each one of which is configured to store a status of a corresponding one of the LDPC variable nodes circuitry such that it stores a first value when the corresponding one of the variable nodes is unlocked and a second value when the corresponding one of the variable nodes is locked; anda plurality of check node lock registers, each one of which is configured to store a status of a corresponding one of the LDPC check nodes circuitry such that it stores a first value when the corresponding one of the check nodes is unlocked and a second value when the corresponding one of the check nodes is locked.