发明名称 LOGIC ANALYZER
摘要 PURPOSE:To detect a protruding data, unexpectedly generated in a process of changing a value of an input digital signal, by sampling the input digital signal so as to be latched, held and compared with an off set addition data value. CONSTITUTION:A digital signal, output from a measured object, is compared with threshold voltage of a D/A converter 2 by a built-in comparator in a probe 1 to perform logical shaping. An output signal of the probe 1 is sampled in accordance with a sampling clock, selected by a clock selecting circuit 3, and latched held by a sample latch circuit 6. An output signal of the circuit 6 is compared with a preset word to output a detection signal from a word detecting circuit 8 in the case of both the output signal and the word agreeing. An edge of riseup of the sampled signal, output from the circuit 6, is detected by an edge detecting circuit 9. Further, a data of a value, protruded as compared with a data sequence before and after a signal series, is detected by a miscode detecting circuit 25.
申请公布号 JPH04204385(A) 申请公布日期 1992.07.24
申请号 JP19900338229 申请日期 1990.11.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKADA TAKANORI
分类号 G01R13/20;G01R31/28;G01R31/319;G06F11/22 主分类号 G01R13/20
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