METHOD AND DEVICE FOR REDUCING LEAKAGE POWER IN CACHE MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a method and a device for reducing leakage power in a cache memory. SOLUTION: A cache memory 300 comprises a two-bit saturation counter 320-n related to each cache line and an N-bit global counter 310. Each cache line comprises a tag which indicates that a specified block of a main memory 130 is currently stored in the cache line and comprises an effective bit which indicates whether stored data is effective. Gray coding is used to change the state of only one bit in order to minimize operation power consumption by minimizing state transition in a counter 320. Besides, the counter 320 can be performed asynchronously in order to simplify the counter 320 and minimize a transistor count.