HDL SIMULATING METHOD CONSIDERING HARD MACRO CORE HAVING NEGATIVE SETUP/HOLD TIME FOR ELECTRONIC CIRCUIT DESIGN

摘要

PURPOSE: An HDL(Hardware Description Language) simulating method considering a hard macro core having a negative setup/hold time for electronic circuit design is provided to improve correctness of the HDL simulation by acquiring correct timing information for the hard macro core. CONSTITUTION: In case that the negative setup time is present in a timing model, it is judged whether an electronic circuit device for receiving a signal inputted through an input port having the negative setup time is present(S302). When the electronic circuit device is present, the first electronic circuit device having the same setup time as the electronic circuit device and operated by responding to the same phase as a clock signal inputted to the electronic circuit device is generated(S304). The first library including the hard macro core and the first electronic circuit device is generated(S305). The HDL simulation for the first library is performed(S306).