| 摘要 |
A decoder circuit with a matrix of MIS transistors wherein a first group of MIS transistors are provided between a potential supply source line and output leads, the transistors of the first group are connected in series, a second group of MIS transistors are provided between a ground line and the output leads, the transistors of the second group are connected in parallel, and gate electrodes of the first and second groups of transistos are connected directly to or indirectly through inverters to address input lines with a predetermined pattern in order to obtain desired output signals.
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