Current-mode sense amplifier

摘要

The invention relates to a current sense amplifier (103) comprising a reference current input terminal (109), a sense control line input terminal (125), a sense current input terminal (108), a first output terminal (106), and a second output terminal (107). The amplifier further comprises a first NAND gate (100) comprising an output terminal being connected to the first output terminal (106), a second NAND gate (101) comprising an output terminal being connected to the second output terminal (106), a first (T1, T5) and a second (T2, T6) cross coupled inverters, the first inverter comprising a first n-FET (T1) and the second inverter comprising a second n-FET (T2), a transmission gate (104) comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to the sense control line input terminal (125), an AND gate (130) having a first input terminal connected to the first output terminal (106) and a second input terminal connected to the second output terminal (107), a third n-FET (T3) having a gate connected to an output terminal of the AND gate (130), a drain connected to the sense current input terminal, a source connected to ground, wherein a source of the first n-FET is connected to the sense current input terminal and a source of the second n-FET is connected to the reference current input terminal, a first input terminal of the first NAND gate and a first input terminal of the second NAND gate are connected to the sense control line input terminal, the first transmission terminal and a second input terminal of the first NAND gate are connected to an output terminal of the second inverter and the second transmission terminal and a second input terminal of the second NAND gate are connected to an output terminal of the first inverter.

主权项

1. A current sense amplifier comprising:
a reference current input terminal; a sense control line input terminal; a sense current input terminal; a first output terminal; a first NAND gate having an output terminal connected to the first output terminal; a second output terminal; a second NAND gate having an output terminal connected to the second output terminal; a first cross coupled inverter comprising a first n-FET; a second cross coupled inverter comprising a second n-FET; a transmission gate comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to the sense control line input terminal; an AND gate having a first input terminal connected to the first output terminal and a second input terminal connected to the second output terminal; and a third n-FET having a gate connected to an output terminal of the AND gate, a drain connected to the sense current input terminal, and a source connected to ground; wherein a source of the first n-FET is connected to the sense current input terminal and a source of the second n-FET is connected to the reference current input terminal; and wherein a first input terminal of the first NAND gate and a first input terminal of the second NAND gate are connected to the sense control line input terminal; and wherein the first transmission terminal and a second input terminal of the first NAND gate are connected to an output terminal of the second inverter and the second transmission terminal and a second input terminal of the second NAND gate are connected to an output terminal of the first inverter.