| 主权项 |
1. A memory system connectable to a host, comprising:
a nonvolatile memory; a device controller configured to control the nonvolatile memory and to store a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of the host as a cache; and a tag memory including a plurality of entries, each of the plurality of entries being associated with each of a plurality of cache lines of the cache, each of the entries including a tag and a plurality of bitmap flags, the tag indicating which area of the L2P table is stored in a corresponding cache line, each of the plurality of bitmap flags corresponding to each of a plurality of sub-lines included in the corresponding cache line, each of the bitmap flags indicating whether a corresponding sub-line is valid or not, wherein the device controller is configured to: determine, by referring to the tag memory, whether a first cache line, which is associated with a tag including an upper bit portion of a first logical address designated by a command received from the host, is present in the cache or not, and whether a first bitmap flag, which is associated with a first sub-line in the first cache line, indicates validity or not, the first sub-line being a sub-line in which first physical address information corresponding to the first logical address is to be stored; read, when the first cache line is present in the cache and the first bitmap flag indicates validity, the first physical address information from the first sub-line of the first cache line; and read, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, the first physical address information from the L2P table of the nonvolatile memory, transfer the read first physical address information to the first sub-line of the first cache line to partly fill the first cache line, and update the first bitmap flag to a value indicative of validity. |
