发明名称 ROBUST NUCLEATION LAYERS FOR ENHANCED FLUORINE PROTECTION AND STRESS REDUCTION IN 3D NAND WORD LINES
摘要 A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
申请公布号 US2017125538(A1) 申请公布日期 2017.05.04
申请号 US201615086702 申请日期 2016.03.31
申请人 SANDISK TECHNOLOGIES INC. 发明人 SHARANGPANI Rahul;SHUKLA Keerti;MAKALA Raghuveer S.;PERI Somesh;LEE Yao-Sheng
分类号 H01L29/49;H01L21/768;H01L27/115 主分类号 H01L29/49
代理机构 代理人
主权项 1. A method of manufacturing a semiconductor device, comprising: forming a stack of alternating layers comprising insulating layers and sacrificial material layers over a substrate; forming a plurality of memory openings through the stack; forming memory stack structures in the plurality of memory openings, each of the memory stack structures comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a semiconductor channel; forming a backside via trench through the stack of alternating layers; forming backside recesses by removing the sacrificial material layers selective to the insulating layers employing an etchant introduced through the backside via trench; depositing a silicon-containing nucleation layer in the backside recesses; and forming at least one tungsten layer in the backside recesses after deposition of the silicon-containing nucleation layer; wherein control gate electrodes for the memory stack structures are formed at levels of the backside recesses; and wherein each of the control gate electrodes comprises a portion of the at least one tungsten layer.
地址 PLANO TX US
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