发明名称 MEMORY SELECTOR
摘要 PURPOSE:To reduce man-days required for assembling and inspecting by selecting a corresponding signal according to a control signal to supply to the terminal of a different signal, decoding an address designating signal, and supplying to an operating state setting terminal in the terminals of the same signal. CONSTITUTION:A CPU generates the control signal SC corresponding to the type of a RAM 2, in a selection circuit SEL 4, the corresponding signal is selected according to the signal SC to apply to the terminal of the different signal. A decoder DEC 3 decodes the address designating signal AS according to the signal SC and applies to the operating state measuring terminal of the terminals of the same signal. Accordingly, the SEL 4 and the DEC 3 operate in response according to the signal SC and the signal corresponding to the type of the RAM 2 is selected and supplied to the terminal of the same number and different signal. At the same time, the signal corresponding to the type of the RAM 2 of the address designating signals is decoded and applied to the terminal for the operating state setting. Thereby, since the labor for selecting and setting is not required, the number of the processes for assembling and inspecting is reduced.
申请公布号 JPS63171492(A) 申请公布日期 1988.07.15
申请号 JP19870001054 申请日期 1987.01.08
申请人 YAMATAKE HONEYWELL CO LTD 发明人 IBATA KAZUMASA
分类号 G06F12/06;G11C7/00 主分类号 G06F12/06
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