METHODS AND APPARATUS FOR PERFORMING PRODUCT SERIES OPERATIONS IN MULTIPLIER ACCUMULATOR BLOCKS

摘要

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.

主权项

1. A multiplier accumulator block on an integrated circuit, comprising:
first, second, and third inputs directly coupled to external configurable interconnect circuitry that is formed outside of the multiplier accumulator block; an output; a first arithmetic operator stage that receives signals from the first and second inputs; a second arithmetic operator stage that receives signals from the third input and has an output port that is coupled to the output; internal configurable interconnect circuitry that is formed within the multiplier accumulator block and that includes:
a first multiplexer that selects between signals generated from the first arithmetic operator stage and signals generated at the output port of the second arithmetic operator stage.