| 发明名称 |
Test Line Letter for Embedded Non-Volatile Memory Technology |
| 摘要 |
The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character. |
| 申请公布号 |
US2017110201(A1) |
申请公布日期 |
2017.04.20 |
| 申请号 |
US201514883787 |
申请日期 |
2015.10.15 |
| 申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Lien Jui-Tsung;Chu Fang-Lan;Lin Hong-Da;Wu Wei Cheng;Chang Ku-Ning;Wang Yu-Chen |
| 分类号 |
G11C29/02;H01L29/423;H01L23/528;H01L23/544;G01R31/28;H01L29/49;H01L21/28;H01L21/768;H01L21/3213;H01L27/115;H01L29/51 |
主分类号 |
G11C29/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated chip, comprising:
a semiconductor substrate; a test line letter structure arranged over the semiconductor substrate and having one or more trenches vertically extending between an upper surface of the test line letter structure and a lower surface of the test line letter structure; and wherein the one or more trenches are arranged within the test line letter structure to define an opening in the upper surface of the test line letter structure that has a shape of an alpha-numeric character. |
| 地址 |
Hsin-Chu TW |
