发明名称 Technologies for managing power during an activation cycle
摘要 Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.
申请公布号 US9625984(B2) 申请公布日期 2017.04.18
申请号 US201514671750 申请日期 2015.03.27
申请人 Intel Corporation 发明人 Ramachandran Aswin;Raman Arvind
分类号 G06F1/26;G06F1/32;G06F11/07 主分类号 G06F1/26
代理机构 Barnes & Thornburg LLP 代理人 Barnes & Thornburg LLP
主权项 1. A computing device for managing power during a processor core activation cycle, the computing device comprising: a processor control module to (i) determine a number of active processor cores of a processor of the computing device and (ii) receive an activation request for at least one hibernating processor core of the processor of the computing device, wherein the activation request includes a command that the at least one hibernating processor core become active; and a power management module to (i) determine a new operating limit for each active processor core based on the number of active processor cores and the number of hibernating processor cores identified by the activation request, (ii) set an operating limit of each active processor core to the new operating limit, and (iii) cause, in response to the activation request, activation of the at least one hibernating processor core subsequent to setting the operating limit of each active processor core.
地址 Santa Clara CA US