发明名称 |
Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect |
摘要 |
A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect. |
申请公布号 |
US9626320(B2) |
申请公布日期 |
2017.04.18 |
申请号 |
US201314031776 |
申请日期 |
2013.09.19 |
申请人 |
NVIDIA Corporation |
发明人 |
Denman Marvin A.;Ma Dennis K.;Glaser Stephen David |
分类号 |
G06F13/40;G06F13/42;G06F5/06;G06F1/32 |
主分类号 |
G06F13/40 |
代理机构 |
Artegis Law Group, LLP |
代理人 |
Artegis Law Group, LLP |
主权项 |
1. A computer-implemented method for scaling the bandwidth of a processing element to match the bandwidth of an interconnect, the method comprising:
receiving, at a first bandwidth, a first data block from a first processing element, wherein the first processing element operates at the first bandwidth; extracting a first portion of the first data block; inserting discardable values into the first portion of the first data block based on an encoding function associated with a serial mask to generate first expanded data, wherein the serial mask is selected via a negotiation between the first processing element and a second processing element; and transmitting, at a second bandwidth, the first expanded data to the second processing element across the interconnect, wherein the interconnect operates at the second bandwidth. |
地址 |
Santa Clara CA US |