发明名称 Autonomous memory subsystem architecture
摘要 An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.
申请公布号 US9612750(B2) 申请公布日期 2017.04.04
申请号 US201514675172 申请日期 2015.03.31
申请人 Micron Technologies, Inc. 发明人 Eilert Sean;Leinwander Mark;Hulbert Jared
分类号 G06F12/00;G06F3/06;G06F12/02;G06F13/12;G06F13/16;G06F13/38;G06F17/30;G06F9/50;G11C7/00;G11C16/00;G06F12/0831;G11C7/10 主分类号 G06F12/00
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. A memory apparatus comprising: a first autonomous memory device; a second autonomous memory device physically coupled to the first autonomous memory device, at least one of the first and second autonomous memory devices including a scratch pad memory port to couple a memory that is external to the first and second autonomous memory devices, each of the first and second autonomous memory devices including a configuration routing table to keep track of other autonomous memory devices in the memory apparatus, the configuration routing table to store latency cost based on location of an autonomous memory device among the autonomous memory devices communicating with another autonomous memory device among the autonomous memory devices, wherein the first autonomous memory device is configured to initiate instructions to disperse portions of a database to the second autonomous memory device; and a controller having a condition monitoring block to monitor bus traffic between the first and second autonomous memory devices.
地址 Boise ID US