发明名称 Semiconductor device
摘要 A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit delay cells and the second group of unit delay cells may be configured for delaying a phase of a clock by a unit cycle of a reference frequency. The reference frequency may serve as a reference for distinguishing between a first frequency and a second frequency. The semiconductor device may include a reservoir capacitor located adjacent to one or more of the unit delay cells of the first group. Only the first group of the unit delay cells may be used to delay the phase of the clock.
申请公布号 US9608639(B2) 申请公布日期 2017.03.28
申请号 US201514798854 申请日期 2015.07.14
申请人 SK HYNIX INC. 发明人 Choi Hoon
分类号 H03L7/06;H03L7/08;H03L7/081;H03L7/095 主分类号 H03L7/06
代理机构 William Park & Associates LTD. 代理人 William Park & Associates LTD.
主权项 1. A semiconductor device comprising: a plurality of delay lines each comprising a plurality of unit delay cells, wherein the plurality of unit delay cells are divided into a first group of unit delay cells and a second group of unit delay cells, wherein the first group of the unit delay cells are used to delay a phase of a clock by a unit cycle of a reference frequency, and the second group of the unit delay cells are not used to delay the phase of the clock by the unit cycle of the reference frequency, wherein the reference frequency serves as a reference for distinguishing between a first frequency and a second frequency, and wherein the first frequency is a frequency higher than the reference frequency, and the second frequency is a frequency lower than the reference frequency, and a reservoir capacitor selectively located adjacent to only one or more of the unit delay cells of the first group, and wherein the one or more of the unit delay cells of the first group delays the clock having the first frequency.
地址 Icheon-si KR