Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

摘要

A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

主权项

1. A semiconductor device comprising:
a channel region in a semiconductor substrate; a gate electrode over the channel region; a gate insulating film between the gate electrode and the channel region; a source region at one end of the channel region and a drain region at another end of the channel region opposite the first end; a first stress-introducing layer in the semiconductor substrate at each side of the gate electrode; a second stress-introducing layer formed at each side of the gate electrode; and a first side-wall insulating film between the second stress-introducing layer and the gate electrode, the first side-wall insulating film having a first side positioned proximate to the second stress-introducing layer and a second side positioned proximate to the gate electrode, wherein,
a width of a bottom portion of the gate electrode proximate to the semiconductor substrate is different than a width of an upper portion of the gate electrode distal to the semiconductor substrate, andthe second side of the side-wall insulating layer has a curved surface such that a distance between facing portions of the second surface of the side-wall insulating layer at opposite sides of the gate electrode is shorter at a position proximate the semiconductor substrate than a distance between facing portions of the second surface of the side-wall insulating layer at opposite sides of the gate electrode at a position distal from the semiconductor substrate.