High-speed multi-block-row layered decoder for low density parity check (LDPC) codes

摘要

High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

主权项

1. A data storage device comprising:
a non-volatile memory; and a controller operatively coupled to the non-volatile memory, the controller including a decoder that is configured to perform an iterative decoding operation using codeword data read from the non-volatile memory, wherein the decoder comprises:
a first check node unit configured to process a first input associated with a first block row of a layer of a parity check matrix;a second check node unit configured to process a second input associated with a second block row of the layer of the parity check matrix;first processing circuitry configured to receive a buffered second input from a second buffer, a first output of the first check node unit, and a second output of the second check node unit and to output a first result based on a first computation; andsecond processing circuitry configured to receive a buffered first input from a first buffer, the first output, and the second output and to output a second result based on a second computation,wherein a length of a critical path of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.