发明名称 Semiconductor device and method for manufacturing the same
摘要 A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.
申请公布号 US9601566(B2) 申请公布日期 2017.03.21
申请号 US201214439514 申请日期 2012.11.19
申请人 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES 发明人 Zhu Huilong
分类号 H01L29/06;H01L29/78;H01L29/66;H01L29/40;H01L21/28;H01L21/306;H01L21/8238;H01L27/092 主分类号 H01L29/06
代理机构 Christensen, Fonder, Dardi & Herbert PLLC 代理人 Christensen, Fonder, Dardi & Herbert PLLC
主权项 1. A semiconductor device, comprising: a substrate; first and second semiconductor layers stacked in a vertical direction on a substrate, wherein the first semiconductor layer has a lateral recess relative to the second semiconductor layer; an isolation layer formed on the substrate, having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and a gate stack formed on the isolation layer and intersecting the fin, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer, wherein said portion of the isolation layer has a first surface extending in the vertical direction and facing and contiguous to the first semiconductor layer, and also a second surface, opposite to the first surface, extending in the vertical direction and facing and contiguous to the gate dielectric layer.
地址 Beijing CN