TRANSISTOR GAIN CELL WITH FEEDBACK

摘要

A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

主权项

1. A gain cell, comprising:
a write bit line input; a read bit line output; a write trigger input; a read trigger input; a write transistor, comprising a first diffusion connection, a gate connection, and a second diffusion connection, said first diffusion connection being connected to said write bit line input and said gate connection being connected to said write trigger input; a read transistor, comprising a first diffusion connection, a gate connection and a second diffusion connection, said first diffusion connection being connected to said read bit line output and said second diffusion connection being connected to said read trigger input; and a retention element associated with said write transistor and said read transistor, configured to buffer between said second diffusion connection of said write transistor and said gate connection of said read transistor during data retention, and to connect said second diffusion connection of said write transistor to a constant voltage during retention of a first data level at said gate connection of said read transistor and to disconnect said second diffusion connection of said write transistor from said constant voltage during retention of a second data level at said gate connection of said read transistor.