Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

摘要

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

主权项

1. An apparatus comprising:
a plurality of semiconductor pillars situated in a grid, the grid of pillars including rows and columns of pillars; a plurality of select gate drain connections situated around the pillars; a plurality of semiconductor control gate connections situated around the pillars below the select gate drain connections, a plurality of first select gate source connections situated around the pillars below the control gate connection; a plurality of second select gate source connections situated around the pillars below the first select gate source connections; and a drive transistor having a drain coupled to both:
the plurality of select gate drain connections; andthe plurality of first select gate source connections or the plurality of second select gate source connections.